Job Description

Do YOU like challenges ? Do YOU have a fascination and expertise for advanced technology, in a world where the structures on chips are moving towards physical limitations and new devices are being invented? Intel's mission is to shape the future of technology and to help create a better future for the entire world.

By pushing forward in fields like AI, analytics and cloud-to-edge technology, Intel's work is at the heart of countless innovations. With a career at Intel you have the opportunity to help make the future more wonderful for everyone.
We are fearless - we put our customers in the center of everything we do - we work together as one team - we value truth and transparency - we embrace diversity.

Your area of responsibility: As an engineer in Design Implementation Methodology (RTL to GDSII) and Advanced Technologies you will work with your team members to develop and support highly productive SoC methodology and flow solutions in leading edge technology nodes. You will develop, provide and support methodologies to our projects for leadership products. We are looking for enthusiastic, experienced and self-driven engineer in Backend Design Automation who can take care of below main duties and responsibilities:
1) Driving the overall R2G enablement for advanced technologies, interfacing with Intel product teams and flow experts.
2) Develop TechLayer tool and flow settings enabling design partitioning, floor planning, place and route, and clock tree synthesis.
3) Advance Physical Design tools, flows and methods, develop / evaluate and deploy required tools, build methodology using automation and tool development, including anticipating / understanding future project teams needs and requirements.

You will be expected to resolve designer's tool / methodology issues on the path to TapeOut, and providing support for design ramp up through training / documentation. You will require to be involved in interacting with EDA providers and ensuring required tools features available for the projects with high quality.
An excellent background in Physical Design and semiconductors is required, as you will work in close interaction with PDK/library experts, flow development teams, as well as with product design teams.

Qualifications:

Minimum Qualifications:

• BS in Electrical or Computer Engineering with 4+ years' experience or MS in Electrical or Computer Engineering with 4+ years' experience in Physical Design, Synthesis, Place and Route, Timing methodologies and flow development.

Preferred Qualifications:

• Deep Expertise and hands-on experience of industry standard Physical Design EDA tools (Fusion Compiler, Innovus, Prime Time, Voltus, Genus, Tempus, Extraction tool, EM/IR, Redhawk SC etc.)

• Experience in scripting languages, such as, Python, Perl, Tcl and software development.

• Exposure to low power techniques and PPA analysis.

• Experience with advanced Implementation flows and knowledge of foundry PDK requirements.

• Design skills (digital or analogue/mixed signal) would be highly beneficial.

• You should have good aptitude for debugging and design automation.

• Excellent communication, networking, presentation skills and pursuing highest quality standards.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.