Job Description

Do you love crafting elegant solutions to highly complex challenges? Join Apple's Silicon Technologies group and help design and deliver our next-generation, high-performance, power-efficient processors and Systems-on-Chip (SoC). In this role, you will be at the center of ensuring seamless DRAM memory integration across Apple's SoC platforms — directly contributing to the silicon that powers every Apple device.

As our DRAM Design Validation Engineer, you will be ensuring the successful integration of DRAM memories with SoC devices, partnering with cross-functional teams and external vendors to deliver world-class memory solutions.

• Collaborate with design, verification, and integration engineers to ensure memory controller and PHY requirements are clearly defined, covering the full scope of DRAM-based corner cases.
• Partner with Architecture, MCU, DDRPHY, and DRAM vendor teams to develop and validate Apple's main memory features.
• Ensure DRAM simulations meet Apple's performance, power, and reliability requirements.
• Define and fulfill internal and external DRAM silicon and package-level testing needs.
• Debug RMA material with DRAM-related defects, driving root cause analysis and resolution.
• Work closely with DRAM vendors to improve memory performance and power efficiency on Apple systems.
• Drive roadmaps and technical specifications with memory vendors for next-generation technology node devices.

Preferred Qualifications

Strong knowledge of DRAM cell architectures, memory organization, and periphery design for low-power DRAM.
Hands-on experience with LPDDRx I/O characterization and qualification.
Knowledge of advanced packaging technologies (PoP, TSV, etc.) and their impact on DRAM signal and power integrity.
Excellent hardware and software debugging skills.
Proven track record working collaboratively with DRAM vendors.
Strong background in computer architecture.
Programming proficiency in Python.
Excellent interpersonal and teamwork skills, with the ability to communicate complex technical concepts clearly across teams.

Minimum Qualifications

BS Degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in DRAM development.
Experience in DRAM simulation and memory interface verification, with a solid understanding of DDR-PHY and Memory Controller design.
Familiarity with memory test patterns and DRAM reliability principles.
Experience in failure analysis of DRAM devices.
Professional proficiency in English required.