Job Description

Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications.  This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products.  (www.avicena.tech) 

About the role:

We are seeking a highly skilled team member to lead the development and manufacturing transfer of high-speed silicon photodetectors (PDs) optimized for microLED-based multi-terabit-per-second communications. This role focuses on managing critical partnerships and processes to enable the successful development and transfer of photodetectors into high-volume manufacturing working with leading semiconductor fabrication partners. This position is based in Sunnyvale, California. This position starts with a single hire with a plan to grow the team as the company and product develops. This is an ideal opportunity for someone looking to develop into a senior engineering management position.

Responsibilities:

• New PD DesignDevelopment:Lead the development ofinnovative PD designsoptimizedfor our applications. Work with internal and externalresources to design and simulatePD performance. Work with internal resources to characterizePDs.

• Foundry Partnership Management:Lead and manage the foundry partnership, including the transfer of new photodetector designs andoversee any necessaryprocess modifications. Ensure alignment betweenAvicena’stechnicaland businessrequirements and the foundrypartner’scapabilities.

• Wafer Testing Management:Oversee the development and implementation of wafer testing strategies, includingidentifyingand managing external vendors for wafer-level testing. Leverageexpertiseto define andvalidatetest methodologies.

• Final Test Development:Collaborate with vendors to set up and manage final test processes, ensuring robust performance validation of packaged devices.

• Qualification:Work with a multi-disciplinary team toestablishqualificationofAvicena’smanufacturing flows and ultimatequalificationto industry standards.

Qualifications:

• Educational Background:

• • BS, MS, or PhD in Materials Science and Engineering, Electrical Engineering, or Applied Physics.

• Industry Experience:

• • Proven experience managing foundry partnerships or foundry processes.

• • Deep understanding of semiconductor device physics and characterization techniques (e.g., SIMS, XRD, SEM, TEM).

• • Familiarity with semiconductor wafer fabrication processes, including photolithography, thin-filmdeposition, andetching.

• • Experience with packaging technologies, including hybrid bonding and waferstackingis a plus.

• • Ability to manage outsourcing tohigh volume manufacturingpartners.

• Testing Expertise:

• • Ability to oversee high-speed optoelectronics testing, including wafer-level and final test processes.

• Project Management Skills:

• • Excellent interpersonal and communication skills to collaborate with internal teams, manage external vendors, and present complex technical findings.

• • Ability to manage timelines, overcome technical challenges, and drive solutions in a dynamic work environment.