Job Description

• Lead a high-performing team of SoC design engineers in areas such as RTL design, integration, and logic implementation. 
• Drive SoC and subsystem-level design and integration from concept to tape-out. 
• Collaborate closely with Architecture, Verification, Physical Design, and Firmware teams to deliver high-quality silicon. 
• Manage project planning, task allocation, and execution tracking to meet aggressive schedules. 
• Recruit, mentor, and develop engineering talent within the team. 
• Contribute to and enforce best practices in RTL development, verification-readiness, and documentation. 
• Participate in design and architecture reviews to ensure scalability, performance, and power-efficiency goals are met. 
• Coordinate with global teams across multiple locations for design convergence and alignment. 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 
• 15+ years of experience in SoC or ASIC design, with at least 8+ years of experience in a technical leadership or management role. 
• Proven expertise in front-end RTL design using Verilog/SystemVerilog. 
• Experience with SoC integration, bus protocols (AXI/AHB), clock/power/reset domains, and IP integration. 
• Familiarity with synthesis, static timing analysis, and design constraints. 
• Strong understanding of the full silicon development cycle, from spec to tape-out. 
• Excellent communication and team leadership skills. 
• Experience working with geographically distributed teams. 
• Experience with ML/AI accelerators, embedded CPUs (e.g., ARM), and low-power design techniques is a plus.   

• Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.