Responsibilities

Job Responsibilities
Logic Synthesis & Optimization
1.Conduct complex-level and chip-level logic synthesis utilizing mainstream EDA tools, including Synopsys DC/FC and Cadence Genus.
2.Formulate and implement customized synthesis strategies to optimize performance across timing, area and power consumption.
3.Analyze setup and hold time violations, and independently troubleshoot and resolve complex clock domain crossing (CDC) issues to ensure robust timing closure.
Formal Verification
1.Perform logic equivalence check (LEC) between RTL and gate-level netlists via Formality, Conformal and other formal verification tools, ensuring full functional consistency throughout the synthesis process.
SDC Development & Management
1.Develop precise, comprehensive and scalable SDC files to standardize and guide subsequent physical implementation and static timing analysis (STA) flows
Cross-team Collaboration
1.Collaborate closely with front-end design engineers and DFT engineers to fully comprehend design specifications and deliver professional design-for-synthesis suggestions to improve design synthesizability.
2.Cooperate with physical design teams to analyze and resolve critical timing bottlenecks and key implementation issues.

Qualifications

Job Requirements
Mandatory Requirements
Education & Major
1.Hold a Master’s or Doctoral degree in Microelectronics, Integrated Circuit Engineering, Electronic Engineering, Computer Science or other related technical disciplines.
Professional Knowledge
1.Possess solid digital circuit fundamentals and in-depth mastery of CMOS device principles, complete timing analysis theories (covering setup/hold time, clock jitter, clock skew, etc.), as well as low-power design methodologies.
Tools & Programming Skills
1.Proficient in digital design languages including Verilog and SystemVerilog.
2.Familiar with Linux operating environment and skilled in at least one scripting language (Tcl / Perl / Python / Shell) for automated flow development and design debugging.
Design Flow Competency
1.Have a clear understanding of the end-to-end digital IC design flow from front-end RTL development to back-end physical implementation, with a solid grasp of core mid-end design procedures.
Personal Competencies
1.Equipped with strong analytical thinking and independent problem-solving capabilities, rigorous and meticulous working style, as well as excellent cross-team communication and collaborative skills.
Preferred Qualifications
1.Hands-on project experience in IC mid-end or back-end implementation based on mainstream advanced process nodes (28nm, 12nm, 7nm, etc.).
2.Practical engineering experience in UPF-based low-power design and implementation flows.
3.In-depth academic research or project experience focusing on formal verification, logic synthesis, or static timing analysis (STA).