Job Description

The DFT architect / lead engineer serves as a technical authority and strategic lead in designing and deploying industry-leading Design-for-Test (DFT) architectures. This role is responsible for the end-to-end DFT strategy for complex, high-performance SoCs—spanning architectural definition, advanced ATPG/MBIST/LBIST strategies, and silicon lifecycle management. You will drive innovation in test methodology to achieve world-class quality, minimize test cost, and ensure seamless transition from pre-silicon RTL to high-volume manufacturing (HVM).

Your Job

• Architectural Leadership: Define and own the global DFT architecture, including Hierarchical Scan, Compressed ATPG, Memory BIST/Repair (BISR), Logic BIST, and IEEE 1687 (IJTAG) networks for multi-die or chiplet-based designs.
• Test Strategy Optimization: Develop advanced strategies for defect-oriented testing and optimize pattern volumes to balance aggressive coverage targets with tester memory constraints and test time.
• Cross-Functional Integration: Lead the integration of DFT requirements into RTL, Synthesis, and Physical Design (STA/PD) flows. Drive "Design for Manufacturability" (DFM) initiatives to improve yield.
• Silicon Bring-up & Debug: Spearhead post-silicon validation and silicon bring-up. Own the root-cause analysis of complex test failures and provide expert-level debugging of ATE/System-level failures.
• Methodology & Automation: Architect and maintain scalable, high-performance DFT flows using TCL, Python, or Perl. Evaluate and benchmark emerging EDA tool features to stay ahead of technology nodes (5nm/3nm and beyond).
• Mentorship & Influence: Provide technical mentorship to junior and senior engineers. Act as a consultant for RTL/DV/PD/STA teams to proactively address timing or routing issues caused by DFT structures.
• Technical Documentation: Author comprehensive DFT specifications and strategy documents that serve as the "Gold Standard" for current and future project iterations.
• Device Execution: At times, will need to own device execution, lead a team through spec, integration, verification and into silicon bring-up.

Other Responsibilities

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications

• Education: Bachelor’s, Master’s, in Electrical Engineering, Computer Engineering, or related fields.
• Experience: 7+ years of hands-on DFT experience with a proven track record of successfully taping out multiple complex SoCs. Must have silicon debug experience including, 1st silicon bring-up, characterization, customer debug, and ramp to production.
• Tool Mastery: Expert-level proficiency with industry-standard EDA suites (e.g., Synopsys TestMAX/DFTMAX, Cadence Modus, or Siemens/Mentor Tessent).
• Advanced Logic Knowledge: Deep understanding of scan compression architectures, hierarchical DFT, and mixed-signal test integration.
• Scripting: Advanced proficiency in TCL and Python/Perl for developing custom CAD attributes and automating complex EDA flows.
• Problem Solving: Demonstrated ability to solve timing closure issues related to DFT or complex ATPG coverage gaps.

Preferred Qualifications

• Specialized Flows: Experience with Automotive ASIL-D functional safety requirements, including In-System Test (IST) and periodic logic/memory monitoring.
• Advanced Packaging: Knowledge of 2.5D/3D IC testing, TSV probing, or HBM test strategies.
• Yield Analysis: Experience with Volume Diagnostics and Yield Learning tools to drive DPPM reduction.
• Industry Presence: Active participation in technical conferences or a history of contributing to patented DFT innovations.

Expected Salary Range

$153,000.00 - $265,000.00

The exact Salary will be determined based on qualifications, experience and location.