Job Description
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 15 years of experience with design from microarchitecture through implementation with Verilog/SystemVerilog language.
- 10 years of experience in managing teams and groups.
- Experience in microarchitecture, design, verification, logic synthesis, and timing closure.
- Experience working with system design principles for low latency, high throughput, security, and reliability.
- Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
Preferred qualifications:
- Master's degree or PhD in Engineering or equivalent practical experience.
- Experience in micro-architecture and design of AI modules, optimizing their power, performance and area.
- Experience in leading chip development projects and teams and execution.
- Ability to motivate and focus on collaborative teams to achieve testing goals.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities
- Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
- Perform RTL development (e.g., coding and debug in SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
- Lead an edge AI IP design team across definition, implementation and deployment phases, while establishing IP development methodologies sharing unified blocks within the IP design team.
- Author block-level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
