Job Description

A leading global semiconductor company is seeking a Principal Design Verification Engineer to lead complex verification efforts for next-generation silicon designs. The ideal candidate brings deep expertise in functional verification methodologies, a strong background in chip-level DV, and the ability to influence design and verification strategy across a high-performing engineering team.

Key Responsibilities

• Lead functional verification of complex digital IPs and SoC subsystems from specification through silicon signoff
• Develop and own verification plans, testbench architectures, and coverage models for assigned blocks
• Write constrained-random testbenches, assertions, and coverage collectors in SystemVerilog/UVM
• Drive closure on functional, code, and formal coverage metrics
• Collaborate with design, architecture, and physical implementation teams to resolve issues and improve DV efficiency
• Mentor junior and mid-level verification engineers and contribute to team methodology standards
• Evaluate and adopt new tools, EDA technologies, and verification methodologies

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of hands-on digital design verification experience in a semiconductor environment
• Expert-level proficiency in SystemVerilog and UVM
• Strong understanding of digital design concepts including pipelines, buses, memory systems, and interfaces
• Experience with simulation tools (VCS, Questa, Xcelium) and coverage closure flows

Preferred Qualifications

• Experience with formal property verification (JasperGold, VC Formal)
• Exposure to networking, storage, PCIe, or high-speed interface IP verification
• Familiarity with emulation platforms (Palladium, Zebu)
• Prior experience in a Principal or Staff engineer role with cross-team influence

Screening Questions

1. How many years of digital design verification experience do you have, and what types of blocks or SoCs have you verified?
2. What is your level of expertise with SystemVerilog and UVM — have you architected testbenches from scratch?
3. Are you able to work onsite full-time in Santa Clara, CA?