Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 4 years of experience verifying digital logic at RTL using SystemVerilog for ASICs.
• Experience coding in SystemVerilog and using standard verification methodologies (i.e., UVM).
• Experience verifying digital IP or subsystems.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering or Computer Science.
• Experience verifying multimedia or image processing hardware components, specifically Image Signal Processors (ISPs), Display Processing Units (DPUs), display interfaces, or Video CODECs.
• Experience with high-speed bus protocols (e.g., AXI, AHB) and memory subsystems.
• Experience with formal verification (SystemVerilog Assertions (SVA)) or emulation platforms (e.g., Palladium, ZeBu).
• Excellent scripting skills (Python, Perl, or Shell) for automation of verification flows.
• Excellent problem-solving, communication, and collaboration skills.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Multimedia Hardware team designs and validates high-performance subsystems that power Google's consumer devices and infrastructure. We focus on the video, image, and display processing technologies, including Image Signal Processors (ISP), Display Processing Units (DPU), and hardware CODECs (encoder/decoder). Our mission is to deliver industry-leading multimedia experiences with optimal power, performance, and area.

Responsibilities

• Plan the verification of complex digital design blocks within the ISP, DPU, or CODEC subsystems by thoroughly analyzing specifications and collaborating with design engineers to identify key verification scenarios.
• Design, build, and maintain constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Develop comprehensive functional coverage plans and implement them to track verification progress.
• Debug failures in simulation, identify root causes in RTL or testbenches, and work with designers to resolve issues.
• Define and run regression suites, analyze coverage metrics, and drive verification closure towards tape-out.