Design Engineer – Verification
Location: Nanjing
Specific duties include:
- Responsible for verification plan define based on IP design SPEC.
- Lead verification team to achieve the coverage driven verification goals.
- Verification Test-Bench maintain and development.
- Deep understanding on ASIC verification flow, responsible for milestone delivery check
Position Requirements:
- Master degree with 1+ years or bachelor with 2+ years as an experienced digital IC verification.
- Experienced in successful tape-out of ASIC chips
- Familiar to UVM test-bench architecture and experienced on test-bench development.
- Self-motivation with communication skills (spoken and written English and Mandarin)
- Experienced in coding of SV, Perl/Python, Makefile
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
