Job Description

Job Reference L438435V

Job Responsibilities:

• Design custom layout for analog and mixed-signal blocks: LDO, Bandgap, ADC/DAC, PLL, SerDes, CDR, Equalizer, Drive, IO Pad, etc.
• Collaborate with Analog and Physical Design teams to ensure layout meets electrical, performance, and area constraints
• Optimize for IR drop, EM, SI, and ensure compliance with DRC/LVS
• Perform DRC, LVS, ERC, PEX using tools like Calibre
• Ensure compliance with technology rules from major foundries (TSMC, Samsung), supporting advanced nodes 2nm, 4nm, 5nm, 8nm, 14nm, 28nm
• Support tape-out, debug layout issues, and improve internal layout processes.

Job Requirements:Qualifications:

• Bachelor's degree or higher in Electrical Engineering, Microelectronics, or related field.
• Minimum 2 years of experience in Custom Layout Design

Technical Skills:

• Proficient in Virtuoso Layout Editor (Cadence) or Synopsys Custom Compiler
• Hands-on experience with Calibre DRC/LVS/PEX, ICV, StarRCXT
• Solid grasp of analog layout techniques: matching, shielding, common centroid, guard ring, and dummy devices
• Familiarity with FinFET nodes (4nm14nm) and GAAFET (2nm3nm) is a plus.
• Basic scripting skills (Skill, Python, Tcl, Perl) are an advantage.

Soft Skills:

• Strong communication and teamwork.
• Able to work independently and take ownership of tasks.
  

What We Offer:

Competitive salary based on experience and ability

Professional work environment with a clear promotion roadmap

Training & collaboration with Korean R&D experts

Full benefits Social insurance, health insurance, travel allowance

Work on cutting-edge technologies 5nm, 2nm nodes and beyond