Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and singoff tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Static Timing Analysis (STA), physical verification, or electrical checks using industry-standard tools.
• Experience working on high-performance CPU, GPU, or SoC block-level designs in advanced process nodes (e.g., 5nm or below).
• Proficiency in scripting with Tcl or Python for workflow automation and QoR analysis.
• Understanding of power grid design, EMIR constraints, and low-power implementation techniques.

About the job

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.