Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with silicon implementation with a focus on high-performance SoC or ASIC development.
• Experience leading cross-functional teams (physical design (PD), package, power, and design for testing through the tape-out cycle, from architecture to Graphic Data System II (GDSII).
• Experience managing technical relationships with external vendors, ASIC partners, or foundries.
• Experience with Customer Owned Tooling (COT) design models and the specific tests they present compared to traditional ASIC flows.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 12 years of experience with silicon implementation with a focus on high-performance SoC or ASIC development.
• Experience defining implementation roadmaps and influencing decisions at the system and architecture level.
• Experience articulating complex technical risks and status to executive management and cross-functional stakeholders.
• Deep technical understanding of advanced process nodes, packaging technologies, and the trade-offs between PPA, thermal, and signal integrity.
  
• Proven track record of driving complex high-frequency/low-power chips to production with first-pass silicon success.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As the Implementation Technical Lead (TL), you are the technical captain responsible for the physical realization of our next-generation custom silicon. You will own the implementability of the entire chip, driving the convergence of Performance, Power, Area (PPA), thermal, and reliability specifications from architecture to tape-out. In this high-visibility role, you will act as the primary bridge between disparate domains such as physical design, packaging, Power, Design for Testing (DFT), and technology, unifying them into a cohesive execution strategy. You will set the technical direction for internal teams and external vendors, ensuring that complex SoC systems are delivered on schedule with the highest quality.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Drive technical decisions and synchronization across all implementation domains (physical design, package, power, Signal Integrity and Power Integrity (SI/PI), and DFT, resolving complex cross-functional issues that impact chip delivery.
• Own the physical implementation of the entire chip, ensuring the final packaged silicon meets all performance, power, area, thermal, yield, and reliability goals.
• Identify critical blocking issues and implementation risks early, develop and execute mitigation strategies to protect the program schedule and quality.
• Manage technical interactions with ASIC partners and external vendors to ensure their deliverables align strictly with chip requirements and milestones.
• Define the framework for implementation execution, including setting technical directions, establishing milestone criteria, and innovation in methodologies.