Qualcomm Semiconductor Limited
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Roles and Responsibilities
Drive architecture definition and technical strategy for next-generation Ethernet switch ASICs, enabling scalable, high-performance networking solutions.
Define architecture and roadmap for Ethernet switching and packet processing subsystems
Lead design across multiple subsystems (forwarding engine, traffic management, scheduling, resource allocation)
Drive cross-functional alignment with HW, SW, and Product teams on networking features and performance targets
Lead performance analysis, modeling, and trade-off studies for switch architecture
Mentor senior technical leaders and influence organization-wide engineering direction
Ensure successful execution from architecture through silicon delivery
Requirements
Deep expertise in ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow
Deep expertise in Ethernet switch architecture, including:
Forwarding pipelines (L2/L3, ACLs, tunneling)
Traffic management (QoS, scheduling, shaping)
High-performance packet processing and scaling strategies
Proven track record delivering complex SoCs
Strong leadership and cross-functional influence capability
Strong debugging and system-level problem-solving skills
Excellent teamwork, interpersonal and communication skills.
Fluent in Chinese and English both verbal and written.
Ability to work in stressful situations with tight schedules to meet.
Experience
10 to 15+ years ASIC design/architecture experience. Experience in merchant silicon or switching ASIC (e.g., Broadcom/Marvell/Realtek/MTK networking chips) is highly desirable.
Education Requirement
Master's degree in Electrical/Electronic Engineering
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
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