Qualcomm Semiconductor Limited
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
MS/BS in Electrical Engineering, Computer Science, or related field (MS preferred).
3+ years work experience in validation, bring-up, debug, system integration, or networking datapath validation (pre-silicon and/or post-silicon).
Strong experience with scripting/tools for validation automation and lab debug practices.
Experience with emulation-based validation and regression bring-up, and/or post-silicon board-based validation and stability/performance testing.
Hands-on experience in packet-based testing/debug (traffic generation, packet capture/analysis, counters/statistics interpretation) for validating forwarding behavior and performance.
Experience with automation infrastructure and processes development; familiarity with scripts/tools such as C, Perl, TCL, makefiles, and shell scripts.
Familiar with ASIC development.
Analytical Skills – Ability to collect information and identify fundamental patterns/trends in data; gather, integrate, and interpret information from several sources.
Building Trusting Relationships – Ability to build collaborative relationships and deliver on commitments.
Communication – Ability to convey information clearly and accurately to technical and non-technical audiences.
Decision-Making – Ability to make quick, accurate decisions and weigh alternatives based on impact.
Getting Work Done – Organized, planful execution across multiple parallel tasks and dependencies.
Mentoring and Coaching – Ability to mentor, guide, and develop others (including technical leadership without direct reports).
Technical Knowledge – Ability to learn and apply system/SoC and networking datapath knowledge to deliver VI solutions.
Excellent teamwork, interpersonal and communication skills.
Fluent in Chinese and English both verbal and written.
Ability to work in stressful situations with tight schedules to meet.
Executes pre-silicon and post-silicon validation, including bring-up, feature enablement, and regression execution in system environments focused on Packet processing engine (PPE) forwarding plane behavior.
Develops and maintains validation content to cover key forwarding functions and feature areas, and validates silicon functionality through bring-up and targeted test plans.
Executes PPE performance validation for key forwarding paths (e.g., bridging and routing) across packet sizes and representative stress patterns; documents results and flags gaps/risks against targets.
Executes protocol consistency testing by validating PPE behavior with real protocol implementations when used by the project, and reports inconsistencies with actionable debug evidence.
Owns VI strategy and execution for functional, performance, endurance, and stability validation from a system viewpoint (use case driven plus hardware upper bound driven).
Defines validation plan based on MRD/PRD, design specs, and use cases; ensures alignment across model/simulation/emulation/post-silicon test phases and drives closure of coverage gaps.
Leads bring-up and end-to-end validation on emulation and silicon; coordinates with SW/HWS/Design/DV and customer-facing teams on issue triage, root-cause isolation, and resolution tracking.
Develops and maintains validation infrastructure and automation (regressions, dashboards, reusable test frameworks), including enabling unified validation methodology where test cases are shared/correlated among model, emulation, and chip validation.
Collaborates with Design/DV to improve quality early by feeding back system findings into specs, DV test intent, and debug hooks; helps DV improve coverage using VI findings and system scenarios.
Drives protocol consistency validation by testing Packet processing engine (PPE) behavior with real protocol implementations, and ensures consistency expectations are met across environments.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
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