Job Description

Minimum qualifications:

• Bachelor's degree in electrical engineering, computer engineering, computer science, a related field, or equivalent practical experience.
• 4 years of experience with System Verilog and UVM

Preferred qualifications:

• Master's degree or PhD in electrical engineering, computer engineering or computer science, with an emphasis on computer architecture.
• Experience in low-power design verification.
  

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As the ASIC Silicon Design Verification Engineer, you will lead the development of verification content and drive hardware-software co-verification strategies. You will focus on bridging the gap between RTL simulation and emulation platforms.

The world is shifting from AI-enabled to AI-native, and this transformation lies in the Tensor Processing Unit (TPU)powering the Pixel phones. You will be the guardian of the compute power that fuels global innovation from Large Language Models (LLMs) to personalized AI assistants.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

The world is shifting from AI-enabled to AI-native, and this transformation lies in the Tensor Processing Unit (TPU)powering the Pixel phones. You will be the guardian of the compute power that fuels global innovation from Large Language Models (LLMs) to personalized AI assistants.

Responsibilities

• Verify designs using verification techniques and methodologies.
  
• Work cross-functionally to debug failures and verify the functional correctness of the design.
  
• Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.