Job Description

Meta is building custom silicon to power the next generation of infrastructure and consumer hardware, including data center accelerators and wearable devices. The Physical Design team is responsible for translating RTL into manufacturable, high-performance silicon by owning the full physical implementation flow from floorplanning through signoff. In this role, you will drive physical design strategy for complex ASIC blocks, define implementation methodologies, and partner closely with architecture, design, and verification teams to deliver chips that meet aggressive power, performance, and area targets at advanced process nodes.

Responsibilities
Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff across advanced process nodes
* Define and drive physical design methodology, flow development, and best practices across the physical design organization
* Perform and own timing closure, including static timing analysis, timing constraint authoring, and multi-corner multi-mode signoff
* Drive power integrity analysis and optimization, including IR drop, electromigration, and dynamic power reduction techniques
* Collaborate with RTL design and architecture teams to provide physical design feedback on microarchitecture decisions, floorplan feasibility, and design-for-manufacturability
* Partner with custom layout and circuit design teams to integrate analog and mixed-signal blocks into the digital physical implementation flow
* Develop and maintain physical design scripts, automation flows, and runsets to improve team productivity and implementation quality
* Conduct design rule check and layout versus schematic verification, resolving violations in coordination with foundry and design teams
* Evaluate and qualify new EDA tools and process design kits, providing technical recommendations to improve physical implementation outcomes
* Mentor other engineers on physical design techniques, flow improvements, and signoff methodology across the team

Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
* 8+ years of experience in ASIC physical design, including hands-on ownership of full physical implementation flows from floorplanning through tapeout
* 8+ years of experience with industry-standard EDA tools for placement, routing, clock tree synthesis, and signoff (e.g., Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre)
* Experience with static timing analysis, timing constraint development, and multi-corner multi-mode closure at advanced process nodes (7nm or below)
* Experience defining and improving physical design methodologies, flows, and automation scripts at an organizational level
* Experience collaborating cross-functionally with RTL design, circuit design, and verification teams to resolve physical implementation challenges Familiarity with low-power design techniques including power gating, multi-voltage domain implementation, and dynamic voltage and frequency scaling
* Proficiency in scripting languages such as Python or Tcl for EDA flow automation and physical design data analysis
* Experience with 3D-IC, chiplet integration, or advanced packaging physical design considerations
* Experience with physical implementation of machine learning accelerators, network-on-chip architectures, or high-bandwidth memory interfaces