Job Description

ASIC Design for Test (DFT) Engineer – Job Description

We are seeking a highly motivated ASIC DFT Engineer to join our Memory PHY development team and drive DFT implementation activities. The successful candidate will be responsible for architecting, implementing, and validating test methodologies to ensure high manufacturing quality, fault coverage, and production yield.

Key responsibilities include defining and implementing DFT features such as Scan, Compression, MBIST, LBIST, Boundary Scan (JTAG), and ATPG flow development. The engineer will collaborate closely with Design, Verification, Physical Design, and Product Engineering teams throughout the ASIC development lifecycle. Responsibilities also include DFT synthesis, scan insertion, pattern generation, fault coverage analysis, test timing closure, and silicon bring-up support.

Experience requirement:

• BS/MS degree in Electrical Engineering or Computer Engineering
• 3+ years of experience in DFT
• Hands-on experience with DFT flows and tools
• It’s a plus if good understanding of HBM, DDR, UCIe protocols
• Good communication in both Mandarin and English