Job Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience with SystemVerilog (SV) and Universal Verification Methodology (UVM).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in low-power design verification.
  

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work in the verification of Google’s SOC offerings. You will collaborate with hardware architects and design engineers for functional and performance verification of the infrastructure IP, interconnects, caches, memory management and system services. You will also work in developing high performance VIPs for protocols supported by our SOCs, and closely collaborate in the deployment of the verification stack across a heterogeneous set of IPs.You will build and verify a generalized class of system topology abstractions, and develop the associated methodologies and tools needed to solve the problem.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Verify designs using verification techniques and methodologies.
  
• Work cross-functionally to debug failures and verify the functional correctness of the design.
  
• Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.