FWe are looking for a Junior ASIC Back-End (Physical Design) Engineer to join our silicon design team. The ideal candidate is a recent graduate or early-career engineer with a strong foundation in VLSI concepts and an interest in ASIC physical implementation and timing closure.
You will work closely with seasoned physical design engineers on block- and chip-level implementation, learning industry-standard flows and tools on advanced 2nm and below tech nodes.
Minimum Qualifications
Preferred Qualifications
AI is transforming industries at an unprecedented scale - but today’s data center infrastructure wasn’t built to keep up. As AI workloads grow more complex and data volumes double every two years, connectivity - not compute - has become the bottleneck.
Retym is solving this challenge by delivering next-generation Coherent DSP solutions that provide high-performance, low-latency connectivity for AI infrastructure and data center interconnects.
We are a semiconductor company driven by innovation, bringing together a world-class team of chip designers, optical networking experts, and leading investors to rethink how data moves in the AI era. Our purpose-built DSP technology delivers:
Scalable, high-bandwidth interconnects for AI-driven data centers
Power-efficient, high-performance networking that removes bottlenecks
A coherent DSP provider that gives module makers more control and builds toward a more open, vibrant ecosystem
With hyperscalers deploying AI across multiple locations and AI infrastructure requirements rapidly evolving, Retym is building the connectivity backbone for the future of AI.
The future of AI isn’t just about compute - it’s about how we move data.
Together, we are building a novel semiconductor technology that will transform the datacenter and telecommunications industries.
