Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Analog/Mixed Signal Lead CAD Engineer

Responsibilities

• Develop, maintain, and optimize analog back-end CAD flows, environments, and automation tools.
• Support key verification flows for analog/mixed-signal projects, including DRC, LVS, QRC, EMIR, and PERC.
• Troubleshoot and resolve issues related to CAD flows, PDKs, and EDA tools.
• Work closely with design, layout, process, and external vendor teams to improve flow stability and design efficiency.
• Contribute to CAD methodology development and flow standardization.

Qualifications

• Bachelor’s degree or above in Microelectronics, Semiconductor Physics, Computer Science, or a related field.
• 5+ years of relevant experience with a bachelor’s degree, or 3+ years with a master’s degree.
• Strong hands-on experience in analog back-end design or CAD support.
• Familiarity with one or more industry-standard tools such as Cadence Virtuoso, Calibre/Pegasus, xCalibre, Quantus, or StarRC.
• Proficiency in scripting languages such as Tcl, Python, Perl, SKILL, or Shell. Strong problem-solving, communication, and teamwork skills.
• Experience in DRC/LVS/PERC rule deck development or PCell development is a plus.

模拟/混合信号 Lead CAD 工程师

岗位职责

• 负责模拟后端 CAD 流程、环境及自动化工具的开发、维护与优化。
• 支持模拟/混合信号项目中的关键验证流程，包括 DRC、LVS、QRC、EMIR 和 PERC。
• 定位并解决与 CAD 流程、PDK 及 EDA 工具相关的问题。
• 与设计、版图、工艺及外部供应商团队紧密合作，提升流程稳定性和设计效率。
• 参与 CAD 方法学建设和流程标准化工作。

任职要求

• 微电子、半导体物理、计算机或相关专业本科及以上学历。
• 本科需 5 年及以上相关经验，硕士需 3 年及以上相关经验。
• 具备扎实的模拟后端设计或 CAD 支持经验。
• 熟悉一种或多种主流工具，如 Cadence Virtuoso、Calibre/Pegasus、xCalibre、Quantus 或 StarRC。
• 熟练掌握 Tcl、Python、Perl、SKILL 或 Shell 等脚本语言中的一种或多种。 具备良好的问题分析能力、沟通能力和团队合作能力。
• 有 DRC/LVS/PERC rule deck 或 PCell 开发经验者优先。

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