Job Description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You bring extensive experience in analog circuit design with a proven track record of delivering silicon-validated IP. Your expertise spans the complete design cycle, from initial architecture through post-silicon validation, and you understand the critical details that differentiate circuits that perform reliably in production from those that merely pass simulation. You have developed proficiency in managing the complexities of high-voltage design, cross-domain integration, and process variation analysis across multiple technology nodes.

Your technical depth extends to understanding the underlying physics of non-volatile memory operation, device stress mechanisms, and reliability considerations that govern long-term performance. You have successfully navigated the challenges of porting analog designs across process nodes, recognizing that technology migration requires careful re-evaluation of device characteristics, design margins, and verification strategies.

You demonstrate strong collaborative capabilities, working effectively with cross-functional teams including layout engineers, digital designers, and verification specialists. Your approach to problem-solving is methodical and thorough, balancing analytical rigor with practical engineering judgment.

At Synopsys, you will contribute to the development of non-volatile memory IP deployed across a broad spectrum of process technologies from advanced 2nm nodes to mature 180nm processes.

What You'll Be Doing

• Design and develop analog circuit blocks for non-volatile memory IP, including charge pumps, high-voltage switches, sense amplifiers, bandgap references, bias generators, low-dropout regulators, and oscillators
• Conduct comprehensive pre-layout and post-layout simulation campaigns across process, voltage, and temperature corners, including Monte Carlo analysis, aging effects, and electromigration and IR-drop verification
• Support IP-level integration activities, addressing analog-digital interface requirements, power domain architecture, multi-supply coordination, and technology node portability across the 2nm to 180nm range
• Collaborate with physical design teams to execute design rule checking, layout versus schematic verification, parasitic extraction, and mixed-signal co-simulation
• Contribute to reliability analysis and qualification programs, including gate-oxide stress evaluation, hot carrier injection assessment, bias temperature instability characterization, electrostatic discharge protection, latch-up prevention, high-temperature operating life testing, data retention validation, and program-erase endurance verification
• Prepare comprehensive IP documentation and deliverables, including technical datasheets, behavioral models in Verilog and Liberty formats, physical views in LEF and GDS formats, and customer integration guidelines

The Impact You Will Have

• Your circuit implementations will directly influence the yield, data retention characteristics, endurance performance, access speed, power consumption, and silicon area efficiency of non-volatile memory IP deployed across multiple foundry partnerships
• You will contribute to improved correlation between pre-silicon simulation and post-silicon measurement, reducing qualification cycle time and minimizing the risk of design iterations
• Your attention to circuit robustness under high-voltage stress and low-voltage operating conditions will enable deployment in automotive, industrial, and consumer applications with stringent reliability requirements
• You will support the development of scalable IP architecture that addresses customer requirements across both advanced and mature process nodes
• Your rigorous approach to corner coverage and statistical analysis will enhance first-silicon success rates and reduce the frequency of costly re-fabrication cycles
• You will help establish reusable design methodologies and IP components that can be efficiently adapted across foundries and technology generations
• Your cross-functional collaboration will strengthen the overall quality, completeness, and time-to-market performance of non-volatile memory IP offerings

What You'll Need

• Bachelor's degree, Master's degree, or PhD in Electrical Engineering, Microelectronics, or a closely related technical discipline
• Minimum of four years of professional experience in analog or mixed-signal integrated circuit design, with demonstrated participation in at least one successful tape-out
• Comprehensive understanding of CMOS technology fundamentals, MOSFET device physics, and analog circuit design principles including operational amplifiers, voltage references, voltage regulators, and timing circuits
• Proficiency with industry-standard electronic design automation tools including Cadence Virtuoso, Synopsys Custom Compiler, Spectre, HSPICE, and Calibre for schematic capture, circuit simulation, and physical verification
• Demonstrated experience designing circuits across multiple process technology nodes, with understanding of how device behavior and design constraints evolve with technology scaling
• Familiarity with silicon characterization procedures, laboratory measurement techniques, and methodologies for correlating measured silicon performance with simulation predictions
• Experience in high-voltage circuit design, non-volatile memory IP development (OTP, MTP, eFuse, Flash, EEPROM technologies), design across both advanced and mature process nodes, mixed-signal verification methodologies, or automotive and high-reliability application domains represents a significant advantage

Who You Are

• You possess strong analytical capabilities that enable you to diagnose simulation failures efficiently, distinguishing between layout-induced issues, device model limitations, and fundamental circuit design concerns
• You communicate technical concepts effectively across disciplines, articulating analog design constraints and requirements to digital designers, layout engineers, and product management stakeholders
• You apply rigorous verification methodologies, understanding which process corners merit detailed analysis, which statistical simulations provide meaningful insight, and when simulation results warrant further investigation despite nominal compliance
• You demonstrate effective collaboration across geographically distributed teams, conveying technical information clearly through both written documentation and verbal presentation
• You maintain organized project management practices, tracking multiple design blocks at various stages of maturity while meeting established milestones and deliverable commitments
• You exhibit intellectual curiosity regarding failure mechanisms, investigating the root causes of reliability concerns, test anomalies, or performance limitations rather than implementing superficial corrections

The Team You'll Be Part Of

You will join the Non-Volatile Memory IP team focused on OTP and MTP memory development. You will work closely with technical leads, layout engineers, digital integration teams, and verification engineers from concept through silicon bring-up. The team operates globally and supports a wide range of process technologies and foundry partnerships.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.