Job Description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years designing circuits that have to work at speeds most people cannot even measure, and you have learned that the difference between a SerDes that ships and one that does not is usually buried in a layout decision or a mismatch calculation someone else would have glossed over. You think in tradeoffs, power versus area versus performance, and you know how to make those calls without waiting for perfect data.

You are the person who can look at a standards document, translate it into block specs, and then actually build the circuit that meets them. You have taped out silicon that works, not just simulations that look good, and you understand what it takes to get from schematic to validated hardware. Layout parasitics, ESD, aging, IR drop, these are not footnotes to you, they are part of the design from day one.

You are comfortable leading a handful of designers through a macro-level build, reviewing their work, catching issues early, and mentoring without micromanaging. Lately, you have been exploring how AI and automation can make your design flow faster and smarter, and you are ready to push that further in a team that takes it seriously.

At Synopsys, you will work on multi-Gbps SerDes IP in the latest FinFET nodes, and what you design will end up in products that move data across the world.

What You'll Be Doing

• Own analog macro-level design for multi-Gbps NRZ and PAM4 SerDes IP, driving architecture, specifications, and circuit implementation from standards to silicon
• Track and review the work of sub-block designers, ensuring power, performance, and area targets are met across TX, RX, and clock path circuits
• Develop and refine circuit implementations for SerDes building blocks including equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, PLLs, DLLs, bandgap references, ADCs, and DACs
• Oversee physical layout in FinFET CMOS to minimize parasitics, device mismatch, proximity effects, and ensure compliance with ESD and reliability requirements
• Collaborate with digital RTL engineers to develop calibration, adaptation, and control algorithms that integrate with your analog circuits
• Drive the adoption of AI-assisted design methods by developing AI agents and Python-based automation that integrate with EDA tools, simulation flows, and design data pipelines to optimize circuit sizing, biasing, and tradeoffs
• Use AI-enabled workflows to reduce manual effort in schematic design, verification, layout review, regression analysis, and silicon correlation, ensuring all AI-generated recommendations are traceable and validated

The Impact You Will Have

• Your macro-level designs will directly enable high-speed connectivity in AI, automotive, and data center products used globally
• The circuit architectures and design strategies you define will set the foundation for future SerDes IP generations across Synopsys portfolios
• Your leadership and mentorship will accelerate the growth and output of junior analog designers on the team
• The AI workflows and automation you build will reduce design cycle time and improve quality across the analog and mixed-signal R&D organization
• Your layout optimization and reliability-focused design practices will result in higher yield and longer product lifespans in the field
• The simulation strategies and verification methods you propose will catch issues earlier and reduce costly silicon respins
• Your collaboration with digital, verification, and CAD teams will improve cross-functional integration and product delivery timelines

What You'll Need

• Master's or PhD in Electrical Engineering, Electronics, or related field with 6+ years of hands-on SerDes or high-speed analog design experience
• Silicon-proven experience implementing circuits for TX, RX, and clock paths within a SerDes, with at least one successful tape-out in a modern process node
• Deep expertise in transistor-level CMOS circuit design with demonstrated ability to optimize FinFET layouts for parasitics, mismatch, and reliability
• Experience leading a small team of designers collaborating on macro-level analog design, including tracking progress and reviewing sub-block work
• Detailed design experience with multiple SerDes sub-circuits such as receive equalizers, data samplers, voltage or current-mode drivers, serializers, deserializers, VCOs, phase interpolators, PLLs, DLLs, bandgap references, ADCs, or DACs
• Hands-on experience applying AI, ML, generative AI, or optimization techniques to analog circuit design, simulation, verification, or design-data analysis; experience building AI agents or Python-based automation that interfaces with EDA tools and simulation environments is a strong plus
• Proficiency with EDA tools for schematic entry, physical layout, and design verification, plus working knowledge of SPICE simulators, Verilog-A, and scripting languages including TCL, Perl, Python, C, or MATLAB

Who You Are

• You can explain a complex circuit tradeoff to a cross-functional team in two sentences without losing the technical nuance
• You review layout with an eye for what will break in silicon, not just what passes DRC, and you catch parasitic issues before they become respins
• You mentor junior engineers by showing them how you think through a problem, not just handing them the answer
• You are comfortable working in ambiguity, whether that means incomplete specs, evolving standards, or early-stage AI tooling that is still being proven out
• You document your designs clearly enough that someone else can pick up your work six months later and understand your intent
• You push back when a simulation plan is too shallow or a layout does not account for aging and mismatch, and you do it in a way that moves the team forward

The Team You'll Be Part Of

You will be part of a growing analog and mixed-signal R&D team developing high-speed analog integrated circuits in the latest FinFET process nodes. The team works on SerDes IP exceeding 200Gbps and collaborates closely with digital designers, verification engineers, and an experienced CAD and software team. The environment includes a full suite of best-in-class IC design tools supplemented by custom, in-house automation.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.