Job Description

Role: Analog and RF layout engineer

Work location: Sunnyvale, CA

Job Type: Contract

Interview: Phone/Skype

• Minimum 6+ years of experience in Analog and RF layout.

• Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level.

• Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.

• Experience with layout of high-performance high-speed analog mixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs.

• Experience with floor planning, block level routing and top-level chip assemble.

• Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration.

Key Responsibilities:

developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level

What are the Mandatory skills and skill proficiencies required for this position?

advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. Experience with floor planning, block level routing and top-level chip assemble. Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.

What are the Optional skills and skill proficiencies for this position?

Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration.

Additional Information

All your information will be kept confidential according to EEO guidelines.