Job Description

As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. You’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned.

You will join an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Machine Learning Engineers!

Imagine yourself at the center of our SOC design effort, collaborating with all fields, getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers.

In this critical and high-visible role, there are tremendous opportunities to extend the power of machine-learning technology into circuit domain and bring groundbreaking innovations to the best silicon design team in the world. You will perform the following:

- Play a strategic role of applying AI/machine-learning techniques to your (and colleagues’) daily work, including circuit design analysis, characterization, QA, and silicon debug.

- Explore areas in custom circuit design and identify initiatives to apply AI technologies.

- Define the goal and spec for each initiative.

- Provide end-to-end solutions, from ideas to implementation.

- Benchmark the return on investment (ROI) with measurable metrics: improved designs, higher efficiency, better quality control, faster turnaround time, etc.

Preferred Qualifications

MS and a minimum of 10 years of VLSI industry experience
Experience of using AI/ML techniques to achieve better PPA of circuit design, higher workflow efficiency, and better quality in deliveries

Minimum Qualifications

MS and a minimum of 5 years of VLSI industry experience
Basic knowledge of digital circuit behavior, PPA tradeoffs, and timing/power/noise modeling