- 20+ years of experience in digital IC implementation including floorplan, power-plan, placement, CTS, routing, SI & STA signoff.
- Hands-on experience on running advanced process below with hierarchical, timing driven, SI prevention, low power place-and-route projects a big plus
- Familiar with SOC-E, STA (ETS or PrimeTime-SI), RC extraction, LEF generation with Abstract generator
- Knowledge of Linux and tcl is a must - Good program / engagement management skill
- Effective team player, willing to learn - Good command of English (written or oral)
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
